Faculty: Prof. Santanu Mahapatra (DESE) and Prof. Soumyendu Raha (CDS)
Atomistic quantum transport simulators are crucial for early‑stage development of next‑generation transistor technologies, where drift-diffusion-based semi-classical models fail. By combining density-functional theory (DFT) based electronic structure with non‑equilibrium Green’s functions (NEGF), they capture quantum confinement, tunnelling, contact resistance, and realistic electrostatics in ultrascaled devices, including multi‑gate, 2D‑material, and memristor architectures. Their atomistic resolution allows explicit treatment of defects, interfaces, strain, and disorder, enabling reliable prediction of I–V characteristics, mobilities, leakage, thermoelectric response, and photocurrent under operating bias. Because these tools can efficiently explore large design spaces of materials, geometries, and bias/gate conditions before fabrication, they guide experiments toward the most promising options, shortening development cycles and reducing cost. They also provide key parameters (e.g., effective masses, scattering rates, mobility limits) for higher‑level TCAD and compact models, forming a quantitative link from quantum materials physics to circuit‑level performance, and supporting continued transistor scaling beyond traditional silicon CMOS.
Developing such a simulator is highly challenging and requires interdisciplinary skill sets. Key challenges include: self‑consistent DFT/NEGF for large devices, fine k‑ and energy meshes, computing electron–phonon coupling, large sparse matrix inversions with high memory demand, robust finite‑bias convergence, efficient parallel scaling, and systematic benchmarking across materials and architectures while keeping runtimes practical for design exploration.
Prof. Mahapatra’s group at DESE has long-standing experience in building quantum-transport simulators [1,2]. Their existing framework, however, is based on low‑energy k·p Hamiltonians with electron–phonon scattering treated via deformation‑potential theory. The next goal is a major upgrade: MLWF‑based atomistic Hamiltonians combined with tile‑based GPU acceleration. Prof. Raha’s group at SERC will provide complementary expertise in scientific computing [3].
Planned methodological developments include (but are not limited to):
- Nested‑dissection solvers for ultra‑large block‑diagonal matrices
- GPU‑compatible finite‑element methods
- Inclusion of electron–phonon, electron–electron, and electron–impurity scattering
- Modelling of ferroelectric memories
- Machine learning acceleration
Learning Outcomes:
Students on this project will gain rigorous training in electronic structure theory, semiconductor device physics, nanotechnology, scientific computing, and GPU programming—skills highly sought in the semiconductor and EDA industries. The project is designed to lead to publications in top journals, positioning students competitively for postdoctoral positions in leading international laboratories.
Prerequisites
Linear algebra, Quantum mechanics, Semiconductor preliminaries, C/C++ coding skills and motivation for scientific software development.
References:
- Sirsha Guha, Sitangshu Bhattacharya and Santanu Mahapatra, “Exceptional Ballisticity in Monolayer BX (X= P, As, Sb) Transistors”. Journal of Applied Physics, Vol. 137, pp. 094302, 2025.
- Madhuchhanda Brahma, Arnab Kabiraj, Marc Bescond and Santanu Mahapatra, “Phonon limited anisotropic quantum transport in phosphorene field effect transistors” Journal of Applied Physics, Vol. 126, No. 114502, 2019.
- Merchant F, Vatwani T, Chattopadhyay A, Raha S, Nandy SK, Narayan R. Efficient realization of householder transform through algorithm-architecture co-design for acceleration of QR factorization. IEEE Transactions on Parallel and Distributed Systems. 2018 Feb 7;29(8):1707-20.