Compiling for Massively Parallel Multi-grain Reactive Computation Models

Faculty: S Raha (CDS), S. K. Nandy (CDS) and J Lakshmi (SERC)

Multi-grain architectures are computing solutions that offer performance and power efficiency comparable to custom hardware implementations coupled with the flexibility of a general purpose processing platform. They are amenable to exploiting different forms of parallelism and can becustomized for domains of computations. REDEFINE is one such massively parallel macro-dataflow architecture which can exploit the  entire spectrum of parallelism granularity. The architecture serves as a template to design and customize accelerators. Domain customization of the architecture combined with a software stack ensures power and performance efficient execution of applications. The thesis will involve exploring  a multitude of design choices at the architecture and compilation levels ranging from choice of a reactive programming frontend to the execution model targeting real time critical systems such as reactor simulators, automotive and avionics control,  and online machine learning, etc.